1. Field of the Invention
This invention relates to the fabrication of integrated circuits (IC) and, more particularly, to the fabrication of IC comprising metal oxide semiconductor field-effect transistors (MOSFET) employing 100 nm and shallower junctions.
2. Description of the Prior Art
CMOS field-effect transistors (FET) employing 0.25 mm gate length dimensions will soon be commercially available. Fabrication of such 0.25 mm dimension FETs typically employs ion implantation for silicon doping. However, MOSFETs having reduced gate-length dimensions of only 0.18 mm and lower are currently being developed. Reduction of gate lengths necessitates source-drain junction depth scaling. For the 0.18 mm CMOS technology, these junctions depths are projected, by the Semiconductor Industry Association's "The National Technical Roadmap for Semiconductors" (1995), to be at less than 80 nm Such junctions are difficult to form using ion implantation due to ion-channeling and transient enhanced diffusion.
Incorporated by reference herein is in the article "Two-Step Doping Using Excimer Laser in Boron Doping of Silicon," by T. Akane et al., Jpn. J. Appl. Phys. Vol. 31 (December 1992) Pt. 1, No. 12B, pages 4437-4440, which discloses an alternative means for silicon doping. In this regard, further incorporated by reference herein is the article "A Shallow Junction Submicrometer PMOS Process Without High-Temperature Anneals," by P. G. Carey et al., IEEE Electron Device Letters, Vol. 9, No. 10, (October 1988), pages 542--544.
Also incorporated by reference herein are the articles "Role of Ion Mass, Implant Dose, and Wafer Temperature on End-of-Range Defects," by S. Prussin et al., J. ElectroChem. Soc., Vol. 137, No. 6 (June 1990), pages 1912--1914; "Damage Removal/Dopant Diffusion Tradeoffs in Ultra-Shallow Implanted p.sup.+ -n Junctions," by R. B. Fair, IEEE Transactions on Electron Devices, Vol. 17, No. 10 (October 1990), pages 2237-2241, and "Avoiding End-of-Range Dislocations in Ion-Implanted Silicon," by S. Acco et al., Materials Science and Engineering, B34, (1995) pages 168-174, all of which are directed to ion implantation to effect silicon amorphization.
Were it not for the high thermal conduction in crystalline silicon, ultra-shallow (e.g., less than 100 nm) junction formation would be possible using prior-art projection gas immersion laser doping (P-GILD), due to near surface absorption of the laser light and short laser pulse widths. In this regard, the geometry of an MOSFET device being fabricated results in shadowing and diffraction of the laser light illuminating the device's surface which has a large effect on thermal loading. Unfortunately, the high thermal conduction in crystalline silicon acts to reduce the junction depth at the edges. These thermal conduction effects become apparent as the dimensions of the doped regions approach the thermal diffusion lengths. As a result, the attributes of the doped region are a function of their dimensions and the surrounding geometry. In the case of source/drain doping in a CMOS device, this results in the doped regions not extending up to the gate (negative gate overlap) or the isolation. This presents an unacceptable problem, since device performance suffers due to high parasitic resistances and shorts between the junctions and the wells.